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The present invention relates to a compression/decompression (abbreviated "codec") circuit, in particular an audio codec circuit, with a digital interface, which has a clock generator and an addressing circuit having a frequency divider, for generating a clock signal derived from a master clock, as well as an address generator and a source follower, and a buffer memory is connected to the addressing circuit.
A codec circuit of the type mentioned at the outset is used, for example, ec5d62056f janalat
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